PVT Variation Tolerant Standby Power Reduction Techniques for Sub- micron SRAMs

Suppressing the leakage current in memories in standby mode is the key to save power in modern SoC mobile application. Scaling / to its limits can reduce leakage power 2-5 times. In this paper, we are going explore the literature and propose that in addition to supply scaling, adaptive body biasing can improve PVT variation tolerance to achieve further standby leakage power reduction. 1.0 Introduction One of the negative side effects of technology scaling is that the leakage power of on-chip memory increases dramatically and becomes one of the main challenges for many systems-on-a-chip (SoC) designs in both active and standby mode. For battery-constrained devices, the reduction of the standby leakage power is important for longer battery life. Since SRAMs is the largest component in many modern SoC, its leakage power during standby mode usually dominates the overall standby power of the whole system [4]. Therefore, an efficient memory leakage suppression scheme is critical for the success of ultra low power design. Various techniques have been developed to reduce SRAM leakage power. At the circuit level, dynamics control of substrate-source back bias were exploited to reduce leakage power [6], but this approach requires some layout modifications on the SRAM cell structure, resulting in some area overhead. At the architectural level, leakage reduction techniques including scaling of of idle memory sections ([3], [4]) and using dynamic sleep transistor (DST) to tune virtual ground [5]. These approaches can achieve leakage energy savings by 2-5 times, but the question remains on how to find the lower/higher bound of standby / that still preserves data. Another negative side effect of technology scaling is the increasing transistor threshold voltage variations across memory arrays. In standby mode, conventional 6T SRAM cell will degrade its static noise margin (SNM) harshly across the memory [2]. As the result, we need to add some margins while scaling / such that SRAMs preserves data. Therefore, in order to get the best advantage of rail-torail scaling, it is desirable to reduce leakage current level of SRAMs in the FF corner (FF corner of threshold voltage) to that in the TT/SS corners by using adaptive body biasing. This technique not only reduces the margins in scaling / but also reduces the overall leakage current. Even though there is some area overhead, it is much less than using bit-cells with more 6T (e.g., [1]). In SRAM design, the Data Retention Voltage (DRV) defines the minimum under which the data in a memory is still preserved. Understanding DRV not only gives the insight of VDD scaling but also helps to understand VSS scaling, thus an analytical model of leakage currents mechanism and DRV is reviewed in section 2. The recent discoveries and circuit techniques in reducing leakage power have been discussed and reviewed in section 3. Section 4 shows some simulation results of how 6T bit-cells leakage current and SNM varies across process variation, rail-to-rail supply scaling, and body biasing. Rail-to-rail supply scaling with adaptive body biasing is proposed in section 5. Finally section 6 concludes our finding and future works. 2.0 Leakage Current and DRV models As shown in Fig. 1, there are three kinds of leakage current: sub-threshold leakage, gate leakage, and junction leakage. When is reduced to DRV, the sub-threshold leakage dominates, thus the destruction of cell data (hold failure) in standby mode is a strong function of the subthreshold leakage of NMOS transistor connected to the node storing “1” [3]. When an SRAM cell is in standby mode, the currents at the storage nodes are balanced. Node : + = , (1) Node : + = , (2) Assuming that = 0 and = (3) Since the bit-lines are set to , is negligible and Eq. 2 becomes: Node : = , (4) In Eqs. (1, 2, 4), is the current of the transistor (Fig. 1) in the sub-threshold region, thus can be modeled as exponential function as in BJT [3]: = e ." #$%& ' . e ()." #$%& '. 1 − e,.)." %& /' (5) where Si is the transistor (W/L) ratio; I0 is a process-specific current at VGS=Vth for a transistor with W/L=1; T is the chip temperature; and ni is the sub-Vth factor (~60mV at room temperature). We further define: 0 = 1234.5 6789 (6) When scales down to DRV, the voltage transfer curves (VTC) of the two storage nodes degrades such that